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MP2661 4.65v system, 500ma,i 2 c-controlled battery charger with power path management for single-cell li-ion battery MP2661 rev. 1.03 www.monolithicpower.com 1 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. the future of analog ic technology description the MP2661 is a highly integrated, single-cell, li-ion/li-polymer battery charger with system power path management for space-limited, portable applications. the MP2661 uses input power from either an ac adapter or a usb port to supply the system load and charge the battery independently. the charger features trickle charge, constant current (cc) and constant voltage (cv) regulation, charge termination, and charge status. the power path management function ensures continuous power to the system by automatically selecting the input, the battery, or both to power the system. this power stage features a low dropout regulator from the input to the system and a 100m ? switch from the battery to the system. power path management separates the charging current from the system load, which allows for proper charge termination and keeps the battery in full-charge mode. the MP2661 provides system short-circuit protection (scp) by limiting the current from the input to the system and the battery to the system. this feature is especially critical to prevent the li-ion battery from being damaged by excessively high currents. an on-chip battery under-voltage lockout (uvlo)cuts off the path between the battery and the system if the battery voltage drops below the programmable battery uvlo threshold, which prevents the li- ion battery from being over-discharged. an integrated i 2 c control interface allows the MP2661 to program the charging parameters, such as input current limit, input voltage regulation limit, charging current, battery regulation voltage, safety timer, and battery uvlo. the MP2661 is available in a 9-pin 1.55mmx1.55mm wcsp package. features ? fully autonomous charger for single-cell li-ion/li-polymer batteries ? complete power path management for simultaneously powering the system and charging the battery ? 0.5% charging voltage accuracy ? 12v maximum voltage for the input source ? i 2 c interface for setting charging parameters and status reporting ? fully integrated power switches and no external blocking diode required ? built-in robust charging protection including battery temperature monitoring and programmable timer ? pcb over-temperature protection (otp) ? system reset function ? built-in battery disconnection function ? thermal limiting regulation on-chip ? available in a wcsp-9 (1.55mmx1.55mm) package applications ? wearable devices ? smart handheld devices ? fitness accessories ? smart watches a ll mps parts are lead-free, halogen-free, and adhere to the rohs directive. fo r mps green status, please visit the mps website under quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks o f monolithic power systems, inc.
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 2 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. typical application table 1:operation mode table items i 2 c control int pin hz=1 ceb=1 fet_dis=1* h to l for 16s h to l for 4s ldo fet off x x x x battery fet (charging) x off off off for 4s, then on on battery fet (discharging) x x off off for 4s, then on on x = no effect * -- fet_dis goes back to 0 battery fet is off.
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 3 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. ordering information part number ** package top marking MP2661gc-xxxx*** wlc sp-9(1.55mmx1.55mm) see below evkt-2661 evaluation kit ** for tape & reel, add suffix ?z (e.g. MP2661gc-xxxx?z) ***?xxxx?is the register setting option. the factory default is ?0000.? this content can be viewed in the i 2 c register map. please contact an mps fae to obtain a ?xxxx? value. top marking ez: product code of MP2661gc y: year code lll: lot number evaluation kit evkt-2661 evkt-2661 kit contents: (items below can be ordered separately). # part number item quantity 1 ev2661-c-00a MP2661 evaluation board 1 2 evkt-usbi2c-02- bag includes one usb to i 2 c dongle, one usb cable, one ribbon cable, 1 3 tdrive-2661 usb flash drive that stores the gui installation file and supplemental documents. 1 order direct from monolithicpower.com or our distributors . evkt-2624 evaluation kit set-up
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 4 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. package reference top view wcsp-9 (1.55mmx1.55mm) pin functions package pin # name i/o description a1 in power input power. place a ceramic capacitor ( 1 f) from in to gnd as close to the ic as possible. a2 sys power system power supply. place a ceramic capacitor ( 2.2 f) from sys to gnd as close to the ic as possible. a3 batt power battery. place a ceramic capacitor ( 2.2 f) from batt to gnd as close to the ic as possible. b1 ntc i temperature sense input. connect a negative temperature coefficient thermistor to ntc. program the hot and co ld temperature window with a resistor divider from vdd to ntc to gnd. the charge is suspended when ntc is out of range. b2 int o open drain interrupt output. int can send the charging status and fault interruption to the host. int is also us ed to disconnect the system from the battery. pull int from high to low for >16s.the battery mosfet is off and turns on automatically after >4s, regardless of the int state. the external pull up resistor at int should be not smaller than 100k ? . b3 vdd i internal control power supply. connect a ceramic capacitor(0.1 f)from vdd to gnd. no external load is allowed. c1 sda i/o i 2 c interface data. connect sda to the logic rail through a 10k ? resistor. c2 scl i/o i 2 c interface clock. connect scl to the logic rail through a 10k ? resistor. c3 gnd power ground.
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 5 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. absolute maxi mum ratings (1) v in ................................................. -0.3v to +13v all other pins to gnd ................... -0.3v to +6.0v continuous power dissipation(t a =+25c) (2) ?..????????????????....1.1w junction temperature ............................ 150c lead temperature (solder) ........................ 260c storage temperature ................ -65c to +150c recommended operating conditions (3) supply voltage (vin) .................... 4.35v to 5.5v (usb input) i in .................................................... up to 455ma i sys .................................................... up to 3a (5) i chg ................................................. up to 455ma v batt ............................................... up to 4.545v operating junction temp. (t j ) ... -40c to +125c thermal resistance (4) ja jc wlcsp-9 (1.55mmx1.55m) .... 114 ... 12 ... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable powe r dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb. 5) guaranteed by design
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 6 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. electrical characteristics v in = 5.0v, v batt =3.5v, t a = +25c, unless otherwise noted. parameter symbol condition min typ max units input source and battery protection input voltage range v in 13 v input operation voltage v in 4.35 5 5.5 v batt input voltage (5) v batt 4.5 v input over-voltage protection (ovp) threshold v in_ovp input rising threshold 5.85 6 6.15 v input ovp hysteresis 350 mv input under-voltage threshold v uv_in input rising threshold 3.8 3.9 4.0 v input under-voltage threshold hysteresis 170 mv input vs. battery threshold v in batt input rising vs. battery 100 130 160 mv input vs. battery threshold hysteresis 85 mv batt under-voltage threshold v uv_batt batt voltage falling, programmable, reg01[2:0]=100 ?2.8v 2.6 2.8 3.0 v battery uvlo range programmable using i 2 c 2.4 3.1 v batt under-voltage threshold hysteresis 210 mv battery over-voltage protection v batt_ovp rising, higher than v batt reg 130 mv falling, higher than v batt reg 70 power path management regulated system output voltage v sys_reg v in =5.5v, i sys =10ma, i chg =0a 4.55 4.65 4.75 v input current limit i in_lmt reg00[2:0]=000 ?85ma 65 75 85 ma reg00[2:0]=001 ?130ma 102 116 130 reg00[2:0]=100 ?265ma 230 247 265 reg00[2:0]=111 ?455ma 400 428 455 input voltage regulation threshold v in_reg i 2 c programmable range 3.88 5.08 v i 2 c setting v in reg =4.20v 4.10 4.20 4.30 sys output voltage v sys charging mode, v in =5.5v, v batt =3.7v 4.55 4.65 4.75 v supplement mode, v batt =3.7v,i batt =100ma 3.6 v in MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 7 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. electrical characteristics (continued) v in = 5.0v, v batt =3.5v, t a = +25c, unless otherwise noted. parameter symbol condition min typ max units in to sys switch on resistance r on_sys v in =5v, i sys =100ma 300 400 m ? supply current at input i in v in =5.5v, ce=l, enable, i chg = 0a, i sys = 0a 600 a v in =5.5v,ce=h, charge disabled 480 supply current at batt input i batt v in =5v, ce=l, i sys =0a, v batt =4.3v 32 a v in =0v, ce=h, i sys = 0a, v batt =4.35v, disable pcb otp function, do not include the current from external ntc resistor 11 13 v in =0v, ce=h, i sys = 0a, v batt =4.35v, enable pcb otp function, do not include the current from external ntc resistor 20 24 v batt =4.5v, v in =v sys =gnd, fet_dis=1, disconnect mode 4 5.5 batt input to sys switch on resistance r on_batt v in < 2v, v batt =3.5v, i sys =100ma 100 150 m ? batt to sys current limit i batt max program range 400 3200 (5) ma batt to sys switch leakage v batt =4.5v, v in =v sys =gnd, disconnect mode 1 a sys reverse to batt switch leakage v sys =6v, v in =4.5v, v batt =gnd, ce=h 1 a battery discharge function controlled by int (5) t int int pull-low lasting time to turn off the battery discharge function 16 s battery mosfet lasts for the off time duration before auto-on 4 battery charger battery voltage regulation range v batt_reg programmable using i 2 c 3.600 4.545 v battery voltage regulation (v batt reg =4.2v) v batt t = +25c, i batt = 15ma 4.179 4.20 4.221 v battery charge full voltage(i 2 c] v batt_reg v batt_reg = 4.2v, reg04[7:2] = 101000 4.179 4.20 4.221 v v batt_reg = 4.35v, reg04[7:2] = 110010 4.328 4.35 4.372
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 8 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. electrical characteristics (continued) v in = 5.0v, v batt =3.5v, t a = +25c, unless otherwise noted. parameter symbol condition min typ max units constant current regulation for charging i chg v in = 5v, v batt = 3.8v, programmable range 8 535 (5) ma v in = 5v, v batt = 3.8v, i chg setting = 93ma 88 93 98 v in = 5v, v batt = 3.8v, i chg setting = 246ma 232 248 263 v in = 5v, v batt = 3.8v, i chg setting = 399ma 376 401 426 charging current thermal foldback threshold (5) junction temperature regulation reg06[1:0]=11?120c 120 c trickle current i tc program range 6 27 ma i tc_setting =6ma, reg03h[1:0]=00 2.5 4.7 i tc_setting =20ma, reg03h[1:0]=10 14 18 22 end of charge (eoc) current threshold i bf i chg_setting 263ma, (reg02 bit[4] = 0), i tc setting = 6ma 5 7 9 ma i chg_setting 263ma, (reg02 bit[4] = 0), i tc setting =13ma 10 13.5 17 i chg_setting 263ma, (reg02 bit[4] = 0), i tc setting =20ma 16 20 24 i chg_setting 263ma, (reg02 bit[4] = 0), i tc setting =27ma 22 27 32 i chg_setting 280ma, (reg02 bit[4] = 1), i tc setting = 6ma 10 13.5 17 i chg_setting 280ma, (reg02 bit[4] = 1), i tc setting =13ma 22 27 32 i chg_setting 280ma, (reg02 bit[4] = 1), i tc setting =20ma 34 42 49 i chg_setting 280ma, (reg02 bit[4] = 1), i tc setting =27ma 46 55 64 end of charge current threshold hysteresis i bf_hys i chg_setting 263ma, (reg02 bit[4] = 0), i tc setting = 20ma 7.5 11 15 ma i chg_setting 280ma, (reg02 bit[4] = 0), i tc setting = 20ma 19 24 29 trickle charge threshold voltage v batt_low v batt rising, set v batt_low =3.0v 2.8 3.0 3.1 v trickle voltage hysteresis 90 mv recharge threshold below v batt_reg v rechg reg04[0] = 0 120 160 200 mv reg04[0] = 1 260 300 350
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 9 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. electrical characteristics (continued) v in = 5v, t a = 25c, unless otherwise noted. parameter symbol condition min typ max units thermal protection thermal shutdown rising threshold (5) 150 c thermal shutdown hysteresis (5) 20 c ntc output current i ntc ce = l, ntc = 3v -100 0 100 na ntc cold temp rising threshold v cold as a percentage of v dd 63 65 67 % ntc cold temp rising threshold hysteresis 30 mv ntc hot temp falling threshold v hot as a percentage of v dd 31 33 35 % ntc hot temp falling threshold hysteresis 70 mv ntc hot temp falling threshold for pcb otp v hot_pcb as a percentage of v dd 30 32 34 % ntc hot temp falling threshold hysteresis for pcb otp 85 mv logic i/o pin characteristics low logic voltage threshold v l 0.4 v high logic voltage threshold v h 1.3 v i 2 c interface(sda, scl) input high threshold level v pull_up = 1.8v, sda and scl 1.3 v input low threshold level v pull_up = 1.8v, sda and scl 0.4 v output low threshold level i sink = 5ma 0.4 v i 2 c clock frequency f scl 400 khz digital clock and watchdog timer digital clock2 f dig2 32 khz watchdog timer t wdt programmable (reg05h [5:4] = 11) 160 s note: (5) guaranteed by design.
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 10 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. typical performanc e characteristics v in = 5v, t a = 25c, i in_lmt =455ma, i chg =246ma, v in_reg =4.76v, unless otherwise noted. 4.182 4.184 4.186 4.188 4.190 4.192 4.194 4.196 4.198 4.200 -50 -30 -10 10 30 50 70 90110130 0.000 1.000 2.000 3.000 4.000 5.000 6.000 7.000 8.000 17.400 17.600 17.800 18.000 18.200 18.400 18.600 18.800 19.200 19.400 19.600 19.800 20.000 20.200 20.400 20.600 20.800 21.000 21.200 21.400 238.000 240.000 242.000 244.000 246.000 248.000 250.000 425.000 430.000 435.000 440.000 445.000 450.000 455.000 4.645 4.646 4.647 4.648 4.649 4.650 4.651 4.199 4.200 4.201 4.202 4.203 4.204 4.205 4.206 4.207 0.000 2.000 4.000 6.000 8.000 10.000 12.000 14.000 16.000 -50 -30 -10 10 30 50 70 90110130 -50 -30 -10 10 30 50 70 90110130 -50 -30 -10 10 30 50 70 90110130 -50 -30 -10 10 30 50 70 90110130 -50 -30 -10 10 30 50 70 90110130 -50 -30 -10 10 30 50 70 90110130 -50 -30 -10 10 30 50 70 90110130 -50 -30 -10 10 30 50 70 90110130
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 11 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. typical performanc e characteristics (continued) v in = 5v, t a = 25c, i in_lmt =455ma, i chg =246ma, v in_reg =4.76v, unless otherwise noted.
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 12 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. typical performanc e characteristics (continued) v in = 5v, t a = 25c, i in_lmt =455ma, i chg =246ma, v in_reg =4.76v, unless otherwise noted.
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 13 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. typical performanc e characteristics (continued) v in = 5v, t a = 25c, i in_lmt =455ma, i chg =246ma, v in_reg =4.76v, unless otherwise noted.
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 14 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. functional block diagram function block diagram
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 15 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. operation introduction the MP2661 is an i 2 c-controlled, single-cell, li- ion or li-polymer battery charger with complete power path management. the full charge function features trickle charge (tc), constant current (cc) and constant voltage (cv) regulation, charge termination, auto-recharge, and a built-in timer. the power path function allows the input source to power the system and charge the battery simultaneously. if there is conflict in meeting both the system load and battery charging current, the ic reduces the charging current automatically or uses the battery as a supplemental power to satisfy the system load. the ic integrates a 300m ? ldo mosfet between in and sys, and a 100m ? battery mosfet between sys and batt. in charging mode, the on-chip 100m ? battery mosfet works as a full-featured linear charger with trickle charging, constant current and constant voltage charging, charge termination, auto-recharging, ntc monitoring, built-in timer control, and thermal protection. the charge current can be programmed via the i 2 c interface. the ic limits the charge current when the die temperature exceeds the thermal regulation threshold (120cdefault). in supplement mode, the 100m ? battery mosfet is fully turned on to connect the battery to the system load when the input power is not enough to power the system load. when the input is removed, the 100m ? battery mosfet is also fully turned on, allowing the battery to power up the system. when the system load is satisfied, the remaining current is used to charge the smart power path management battery. the ic reduces the charging current or uses power from the battery to satisfy the system load when its demand is over the input power capacity. figure 1 shows the power path management structure of theMP2661. figure 1: power path management structure power supply the internal bias circuit of the ic is powered from the higher voltage of in or batt. when in or batt rises above the respective under- voltage lockout (uvlo) threshold, the sleep comparator, battery depletion comparator, and the battery mosfet driver are active. the i 2 c interface is ready for communication and all registers are reset to the default value. the host can access all registers. input ovp and uvlo the MP2661 has an input over-voltage protection (ovp) threshold and an input uvlo threshold. once the input voltage exits the normal input voltage range, the q1 mosfet is turned off immediately. when the input voltage is identified as a good source, a 200 s immunity timer is active. if the input power is still sufficient until the 200 s timer expires, the system starts up. otherwise, q1 remains off. figure 2 depicts the operation profile. figure 2: input power detection operation profile
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 16 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. figure 3: battery charge profile power path management the ic employs a direct power path structure with the battery mosfet decoupling the system from the battery, which allows for separate control between the system and the battery. the system is given the priority to start up even with a deeply discharged or missed battery. when the input power is available, even with a depleted battery, the system voltage is always regulated to v sys_reg by the integrated ldo mosfet. as shown in figure 1, the direct power structure is composed of a frond-end ldo mosfet between in and sys and a battery fet between sys and batt. the input ldo (using an ldo mosfet) provides power to the system, which drives the system load directly and charges the battery through the battery fet. for the system voltage control, when the input voltage is higher than v sys_reg , the system voltage is regulated to v sys_reg . when the input voltage is lower than v sys_reg , the ldo mosfet is fully on with the input current limit. battery charge profile the ic provides three main charging phases: trickle charge, constant current charge, and constant voltage charge (see figure 3). 1. phase 1 (trickle current charge): the ic is able to safely trickle charge the deeply depleted battery until the battery voltage reaches the trickle charge to the fast charge threshold (v batt_low ). the trickle charge current is programmable via reg03 bit [1:0]. if v batt_low is not reached before the pre- charge timer (1hr) expires, the charge cycle is ceased, and a corresponding timeout fault signal is asserted. 2. phase 2 (constant current charge): when the battery voltage exceeds v batt_low , the ic enters a constant-current charge (fast charge) phase. the fast charge current can be programmable via reg02 bit [4:0]. 3. phase 3 (constant voltage charge): when the battery voltage rises to the pre- programmable charge full voltage (v batt_reg ) set via reg04 bit [7:2], the charge mode changes from cc mode to cv mode, and the charge current begins to taper off. assuming the termination function (en_bf)is set via reg05[6] = 1, the charge cycle is considered complete when the following conditions are valid: ? the charge current(i batt ) reaches the end of charge (eoc) current threshold(i bf ), and the 2.5ms delay timer is initiated. ? during the 2.5ms delay period, i batt is always smaller than i bf +i bf_hysteresis . the charge status is marked as complete once the 2.5ms delay timer expires.
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 17 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. the charge current is terminated at the same time if term_tmr is set via reg05[0] = 0; otherwise, the charge current keeps tapering off. if en_bf = 0, the termination function is disabled, the above actions will not occur. during the charging process, the actual charge current may be less than the register setting due to other loop regulations, such as dynamic power management (dpm) regulation (input voltage, input current) or thermal regulation. if the input current or the input voltage reach their limits during the cv charge, the charge full termination is not influenced when the charge current is not so close to the eoc current specification. a new charge cycle starts when the following conditions are valid: ? the input power is recycled ? battery charging is enabled by the i 2 c ? auto-recharge kicks in under the following conditions: ? no thermistor fault at ntc ? no safety timer fault ? no battery over-voltage ? batfet is not forced to turn off automatic recharge when the battery is fully charged and the charging is terminated, the battery may be discharged due to system consumption or self- discharge. when the battery voltage is discharged below the recharge threshold, and v in is still in the operation range, the ic begins another new charging cycle automatically without the requirement of restarting a charging cycle manually. the auto-recharge function is valid only when en_bf =1 and term_tmr=0. battery over-voltage protection (ovp) the ic is designed with a built-in battery over- voltage limit about 130mv higher than v batt_reg . when the battery over-voltage event occurs, the ic suspends the charging immediately and asserts a fault. input current and input voltage based power management to meet the input source (usually usb) maximum current limit specification, the ic uses input current-based power management by monitoring the input current continuously. the total input current limit can be programmed via the i 2 c to prevent the input source from overloading. if the pre-set input current limit is higher than the rating of the input source, back-up input voltage-based power management also works to prevent the input source from being overloaded. if either the input current limit or the input voltage limit is reached, the q1 mosfet between in and sys are regulated so that the total input power is limited. as a result, the system voltage drops. once the system declines to the minimum value of 4.56v or v in - 160mv, the charge current is reduced to prevent the system voltage from dropping further. voltage-based dpm regulates the input voltage to v in_reg when the load is over the input power capacity. v in_reg set via the i 2 c should be at least 400mv higher than v batt_reg to ensure the stable operation of the regulator. battery supplement mode the charge current is reduced to keep the input current or input voltage in regulation when dpm occurs. if the charge current is at zero, and the input source is still overloaded due to a heavy system load, the system voltage starts to fall off. once the system voltage falls below the battery voltage, the ic enters battery supplement mode. when the system voltage is 30mv below the battery voltage, the ideal diode mode is enabled. the battery mosfet is regulated to maintain v batt -v sys at 22.5mv. if the supplement current i dsg *r on_batt is higher than 22.5mv, the battery mosfet is fully turned on to keep the ideal forward voltage. when the system load decreases, once v sys is higher than v batt +20mv, ideal diode mode is disabled. figure 4 shows the dynamic power management and battery supplement mode operation profile.
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 18 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. when v in is not available, the ic operates in discharge mode, and the battery mosfet is always fully on to reduce loss. figure 4: dynamic power management and battery supplement operation profile battery charge full voltage the battery voltage for the constant voltage regulation phase is v batt_reg . when v batt_reg is 4.2v, it has a 0.5% accuracy over the ambient temperature range of 0c to +50c. when the battery is removed, the batt voltage is between v batt_reg -v rechg and v batt_reg . thermal regulation and thermal shutdown the ic monitors the internal junction temperature continuously to maximize power delivery and prevent the chip from overheating. when the internal junction temperature reaches the pre-set limit of t reg (default 120c), the ic reduces the charge current to prevent higher power dissipation. the multiple thermal regulation thresholds from 60c to 120c help the system design meet the thermal requirement in different applications. the junction temperature regulation threshold can be set via reg06 bit [1:0]. when the junction temperature reaches 150c, both q1 and q2 are turned off. negative temperature coefficient (ntc) temperature sensor ntc allows the ic to sense the battery temperature using the thermistor usually available in the battery pack to ensure a safe operating environment for the chip. a resistor with an appropriate value should be connected from vdd to ntc, and the thermistor should be connected from ntc to ground. the voltage on ntc is determined by the resistor divider, whose divide ratio depends on the temperature. the ic sets a pre-determined upper and lower bound of the divide ratio internally for ntc cold and ntc hot. in the MP2661, the i 2 c default setting is the pcb otp. the function can be changed through the i 2 c (see table 2). table 2: ntc function selection table i 2 c control function en_ntc enb_pcb otp 0 x disable 1 1 ntc 1 0 pcb otp when pcb otp is selected, if the ntc voltage is lower than the ntc hot threshold, both the ldo mosfet and battery mosfet are off. the pcb otp fault sets the ntc_fault status (reg08 bit [1]) to 1 to indicate the fault. operation resumes once the ntc voltage is higher than the ntc hot threshold. the ntc function only works in charge mode. once the ntc voltage falls out of the divide ratio (the temperature is outside the safe operating range), the ic stops the charging and reports it on the status bits. charging resumes automatically after the temperature falls back into the safe range. safety timer the ic provides both a pre-charge and a fast- charge safety timer to prevent extended charging cycles due to abnormal battery conditions. the safety timer is one hour when the battery voltage is below v batt_low . the fast charge safety timer begins when the battery enters fast charging. the fast charge safety timer can be programmed through the i 2 c. the safety timer feature can be disabled via the i 2 c.
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 19 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. the following actions restart the safety timer: ? a new charge cycle is kicked in ? reg01 bit [3] is written from 0 to 1 (charge enable) ? reg05 bit [3] is written from 0 to 1 (safety timer enable) ? reg01 bit [7] is written from 0 to 1 (software reset) host mode and default mode the ic is a host-controlled device. after the power-on reset, the ic starts in the watchdog timer expiration state or default mode. all registers are in the default settings. any write to the ic changes it to host mode. all charge parameters are programmable. if the watchdog timer (reg05 bit [5:4]) is not disabled, the host must reset the watchdog timer regularly by writing 1 to the reg01 bit [6] before the watchdog timer expires to keep the device in host mode. once the watchdog timer expires, the ic returns to default mode. the watchdog timer limit can also be programmed or disabled by the host control. when there is no v in , the watchdog timer is suspended. (figure 9) the operation can also be changed to default mode when one of the following conditions occur: ? refresh input without battery ? re-insert battery with no v in ? register reset reg01 bit [7] is reset battery discharge function if battery is connected and the input source is missing, the battery mosfet is fully on when v batt is above the v uv_batt threshold. the 100m ? battery mosfet minimizes conduction loss during discharge. the quiescent current of the ic is as low as 11 a in this mode. the low on resistance and low quiescent current help extend the running time of the battery. over-discharge current protection the ic has an over-discharge current protection in discharge mode and supplement mode. once i batt exceeds the programmable discharge current limit (default 1.785a), the battery mosfet is turned off after a 60s delay, and the MP2661enters hiccup mode in over- current protection. the discharge current can be programmed high to 3.2a through the i 2 c.ifthe discharge current goes high to reach the internal fixed current limit (about 3.7a), the battery mosfet is turned off and starts hiccup mode immediately. similarly, when the battery voltage falls below the programmable v uv_batt threshold (default 2.8v), the battery mosfet is turned off to prevent over-discharge. system short-circuit protection (scp) the MP2661 features sys node short-circuit protection (scp) for the in to sys path and the batt to sys path. the system voltage is continuously monitored. if v sys is lower than 1.5v, the system (scp) for the in to sys path and the batt to sys path are active. i battoc is decreased to half of the original value. 1) in to sys path: once i in is over the protection threshold, both the ldo mosfet and the batt mosfet are turned off immediately, and the ic enters hiccup mode. otherwise, the max current limit and the setting input current limit are not reached, and i in is regulated at i inlmt . hiccup mode also starts after a 60s delay. the interval of the hiccup mode is 800s. 2) batt to sys path: once i batt is over the 3.7a protection threshold, both the ldo mosfet and the batt mosfet are turned off immediately, and the ic enters hiccup mode. when the battery discharge current limit threshold is reached, hiccup mode starts after a 60s delay. the interval of the hiccup mode is 800s. if a system short-circuit occurs when both the input and battery are present, the protection mechanism of both paths work, with the faster one dominating the hiccup operation. (figure 12) interrupt to host (int) the ic has an alert mechanism which can output an interrupt signal via int to notify the system of the operation by outputting a 256 s low-state int pulse. all of the below events can trigger the int output:
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 20 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. ? good input source detected ? uvlo or input ovp charge completed ? charging status change ? any fault in reg08 (watchdog timer fault, input fault, thermal fault, safety timer fault, battery ovp fault, ntc fault) when any fault occurs, the ic sends out an int pulse and latches the fault state in reg08. after the ic exits the fault state, the fault bit could be released to 0 after the host reads reg08. the ntc fault is not latched and always reports the current thermistor conditions. note that the int needs the external pull up resistor for its open-drain connection. suggest the resistance not lower than 100k ? . battery disconnection function in applications where the battery is not removable, it is essential to disconnect the battery from the system: case a: to prevent excessive capacity discharge during the device is in shipping or storage. case b: allow the system power reset the MP2661 provides both shipping mode (see figure 13) and system reset mode for different application requirements. 1). shipping mode: entering the shipping mode : the register bit (fet_dis), reg06 bit[5], controls the ic to enter the shipping mode. during the normal operation, the battery mosfet is turned on and this bit is 0. if this bit is set to 1 through i 2 c, the battery mosfet is turned off, and the MP2661 enters shipping mode. the fet_dis bit is reset to 0 automatically after the battery mosfet is turned off (see figure 5). exiting shipping mode: the ic can exit the shipping mode by pulling int down. 1.1) when the ic is in the shipping mode and only the battery is present, pulling int down by pushing pb (see the "typical application circuit" ) could wake the MP2661 up from shipping mode. (refer to table3) figure 5: the time delay from fet_dis is written (1) to the battery fet off table3 exit the shipping mode with batt present only int signal ic exits the shipping mode case1 int= low twice with the rising edge >600ns at once case2 int= low once with the rising edge >600ns after 4s case3 int= low for 4s once after the 4s case4 int = low with the rising edge in ms level at once 1.2) when the ic is in the shipping mode and a valid vin powers on, the MP2661 could be woken up too. after vin is preset, the MP2661 pulls int low to indicate the event "good input source detected" if the vin is in the operation range. then, the MP2661 could be woken up from the shipping mode by the int signal. (see figure 6). table4 exit the shipping mode with vin powers on int signal ic exits the shipping mode case1 int= low twice with the rising edge >600ns at once case2 int= low once with the rising edge >600ns after 4s case3 int = low with the rising edge in ms level at once
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 21 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. int_gate int_gate _delay int int_ext vin power on 0v 5v 600ns vth t t t t t t int_dly figure 6: int signal during vin powers on if fet_dis is set to 1 during the shipping mode, the ic could still wake up after int keeping low for 4s. but in this case, the fet_dis bit can not be reset to 0 automatically, it has to be reset to 0 manually through i 2 c. 2). reset mode the ic can use int to cut off the path from the battery to the system when system reset is needed. once the logic at int is set to low for more than 16s, the battery is disconnected from the system by turning off the battery mosfet. the off state lasts for 4s, then the battery mosfet is turned on automatically, and the system is powered by the battery again. during the 4s off period, int pin voltage level could be high or low. the ic can reset the system by controlling int (see figure 7). figure 7: system reset function operation profile
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 22 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. i 2 c register map ic address: 09h (reserved some trim options) input source control register/address: 00h (default: 01001111) bit symbol description read/write default bit 7 en_hiz (7) 0:disable 1:enable read/write disable (0) input voltage regulation bit 6 v in reg [3] 640mv read/write offset: 3.88v range:3.88v -5.08v default: 4.60v (1001) bit 5 v in reg [2] 320mv bit 4 v in reg [1] 160mv bit 3 v in reg [0] 80mv input current limit bit 2 i in_lim [2] 000:85ma 001:130ma 010:175ma 011:220ma 100:265ma 101:310ma 110:355ma 111:455ma read/write 455ma (111) bit 1 i in_lim [1] bit 0 i in_lim [0] note: 7) this bit only controls the on and off of the ldo mosfet. power-on configuration register/address: 01h (default: 0000 0100) bit symbol description read/write default bit 7 register reset 0:keep current setting 1: reset read/write keep current setting (0) bit 6 i 2 c watchdog timer reset 0:normal 1:reset read/write normal(0) bit 5 reserved read/write reserved bit 4 reserved read/write reserved charger configuration bit 3 ceb 0: charge enabled 1:charge disabled read/write charge enabled (0) battery uvlo threshold bit 2 v uv batt [2] 0.4v read/write offset: 2.4v range: 2.4v-3.1v default: 2.8v (100) bit 1 v uv batt [1] 0.2v bit 0 v uv batt [0] 0.1v
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 23 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. i 2 c register map (continued) charge current control register/address: 02h (default: 000 01110) bit symbol description read/write default bit 7 reserved read/write reserved bit 6 reserved read/write reserved bit 5 reserved read/write reserved charge current setting bit 4 i chg [4] 272ma read/write offset: 8ma range: 8ma -535ma default: 246ma (01110) bit 3 i chg [3] 136ma bit 2 i chg [2] 68ma bit 1 i chg [1] 34ma bit 0 i chg [0] 17ma pre-charge/termination current/address: 03h (default: 01001 010) bit symbol description read/write default bit 7 reserved read/write reserved batt to sys discharge current limit bit 6 i dch [3] 1600ma read/write offset: 200ma range: 400ma-3.2a valid range: 0001 - 1111 default:2000ma(1001) bit 5 i dch [2] 800ma bit 4 i dch [1] 400ma bit 3 i dch [0] 200ma pcb otp enable bit 2 enb_pcb otp 0:enable 1:disable read/write enable(0) trickle current bit 1 i tc [1] 14ma read/write offset: 6ma range: 6ma-27ma default: 20ma (10) bit 0 i tc [0] 7ma
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 24 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. i 2 c register map (continued) charge voltage control register/address: 04h (default: 1010 0011) bit symbol description read/write default battery regulation voltage bit 7 v batt reg [5] 480mv read/write offset: 3.60v range: 3.60v - 4.545v default: 4.2v (101000) bit 6 v batt reg [4] 240mv bit 5 v batt reg [3] 120mv bit 4 v batt reg [2] 60mv bit 3 v batt reg [1] 30mv bit 2 v batt reg [0] 15mv trickle charge threshold bit 1 v batt_low 0: 2.8v 1: 3.0v read/write 3.0v (1) battery recharge threshold (below v batt reg ) bit 0 v rechg 0: 150mv 1:300mv read/write 300mv (1) charge termination/timer control register/address: 05h (default: 0100 1010) bit symbol description read/write default bit 7 reserved read/write reserved termination setting (the termination is allowed or not) bit 6 en_bf 0:disable 1:enable read/write enabled(1) i 2 c watchdog timer limit bit 5 watchdog [1] 00:disable timer 01: 40s 10: 80s 11: 160s read/write disable timer(00) bit 4 watchdog [0] safety timer setting bit 3 en_timer 0:disable 1:enable read/write enable timer (1) constant current charge timer bit 2 chg_tmr [1] 00:3hrs 01: 5hrs 10: 8hrs 11: 12hrs read/write 5hrs (01) bit 1 chg_tmr [0] termination timer control (when term_tmr is enabled, the ic will not suspend the charge current after charge termination) bit 0 term_tmr 0:disable 1:enable read/write (0)
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 25 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. i 2 c register map (continued) miscellaneous operation control register/address: 06h (default: 0100 1011) bit symbol description read/write default bit 7 reserved read/write read/write bit 6 tmr2x_en 0:disable 2x extended safety timer during ppm 1:enable 2x extended safety timer during ppm read/write enable (1) bit 5 fet_dis (8) 0:enable 1: turn off read/write enabled(0) bit 4 reserved read/write (0) bit 3 en_ntc 0:disable 1:enable read/write enabled(1) bit 2 reserved read/write thermal regulation threshold bit 1 t reg [1] 00: 60c 01: 80c 10: 100c 11: 120c read/write 120c (11) bit 0 t reg [0] note: 8) this bit controls the on and off of the batte ry mosfet, including the charging and discharging. system status register/address: 07h (default: 0000 0000) bit symbol description read/write default bit 7 reserved read only reserved revision bit 6 rev [1] revision number read only (00) bit 5 rev [0] bit 4 chg_stat [1] 00:not charging 01:trickle charge 10: charge 11: charge done read only not charging (00) bit 3 chg_stat [0] bit 2 ppm_stat 0:no ppm 1:inppm read only no ppm (0) (no power-path management happens) bit 1 pg_stat 0:power fail 1: power good read only not power good (0) bit 0 therm_stat 0:no thermal regulation 1:in thermal regulation read only normal (0)
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 26 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. i 2 c register map (continued) fault register/address: 08h (default: 0000 0000) bit symbol description read/write default bit 7 reserved read only reserved bit 6 watchdog_fault 0:normal 1:watchdog timer expiration read only normal (0) bit 5 vin_fault 0:normal 1:input fault (ovp or bad source) read only normal (00) bit 4 them_sd 0:normal 1: thermal shutdown read only bit 3 bat_fault 0:normal 1:battery ovp read only normal (0) bit 2 stmr_fault 0:normal 1:safety timer expiration read only normal (0) bit 1 ntc_fault [1] 0:normal 1:ntc hot read only normal (00) bit 0 ntc_fault [0] 0:normal 1:ntc cold
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 27 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. state conversion chart bfet off bfet on bfet on enable charge bfet off disable charge in plug-in hiz quit p sys > p in p sys < p in in plug-out hiz entry in plug-in hiz quit in plug-out hiz entry figure 8: state machine conversion
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 28 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. control flow chart figure 9: default mode and host mode selection (10) notes: 9) once the watchdog timer expires, the i 2 c watchdog timer must be reset, or the watchdog timer is not valid in the next cycle. 10) the watchdog timer is held when v in is not present.
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 29 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. control flow chart (continued) figure 10: input power start-up flow chart
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 30 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. control flow chart (continued) figure 11: charging process
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 31 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. control flow chart (continued) figure 12: system short-circuit protection
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 32 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. control flow chart (continued) set int_gate from 0 to 1 int_gate=1 delay block 1 reset int_gate from 1 to 0 int_gate=0 set int from 1 to 0, int=0 keep pushing pb low? reset int from 0 to 1 before int<1v, int_dly=0 yes no int_pulse generating block int falling edge delay block 2 latch block a int_ext=fet_dis=0, latch output as 0 int_ext=1,fet_dis=0, latch output as 1 as long as fet_dis=1, latch output as 1 nand gate enable osc & 4s timer 1 is effective 4s timer out? no yes int_pulse=1? yes no latch block b int_ext=fet_dis=0, latch output as 1 int_ext=1,fet_dis=0, latch output as 0 as long as fet_dis=1, latch output as 0 nand gate reset shipping mode block 0 is effective push pb (2 nd ) int_ext=0? & fet_dis=0? int_gate_dly=0 & int_dly=0 yes, int_ext=0 vin power on push pb (1 st ) exist shipping mode reset 4s timer figure 13: MP2661 exits the shipping mode
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 33 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. application information selecting a resistor for the ntc sensor ntc uses a resistor divider from the input source (vdd) to sense the battery temperature. the two resistors (r t1 and r t2 )allow the high temperature limit and low temperature limit to be programmed independently. in other words, the ic can fit most types of ntc resistors and different temperature operation range requirements with the two extra resistors. r t1 and r t2 depend on the type of the ntc resistor and can be calculated with equation (1) and equation (2): ?? ??? ? ??? ? ????? cold hot ntch ntcl t2 hot cold hot ntcl cold cold hot ntch vvrr r vvv r v vv r (1) ?? cold t1 t2 ntcl cold 1-v r(r//r) v (2) where r ntch is the value of the ntc resistor at a high temperature of the required temperature operation range, and r ntcl is the value of the ntc resistor at a low temperature. selecting the external capacitor like most low-dropout regulators, the MP2661 requires external capacitors for regulator stability and voltage spike immunity. the device is specifically designed for portable applications requiring minimum board space and small components. these capacitors must be correctly selected for optimal performance. an input capacitor is required for stability. a capacitor at least 1f must be connected between in and gnd for stable operation over the entire load current range. there can be more output capacitance than input as long as the input is at least 1f. the ic is designed specifically to work with a very small ceramic output capacitor(typically 2.2f). a ceramic capacitor with x5r or x7r type dielectrics at least2.2f is suitable in the MP2661 application circuit. for the MP2661, the output capacitor should be connected between sys and gnd with thick traces and a small loop area. a capacitor from batt to gnd is also necessary for the MP2661, and the typical capacitance value is 2.2f. a ceramic capacitor with x5r or x7r type dielectrics at least 2.2f is suitable for the application circuit. a capacitor between vdd and gnd is used to stabilize the vdd voltage to power the internal control and logic circuit. the typical value of this capacitor is 100nf. pcb layout guidelines efficient pcb layout is critical for stable operation. for best results, follow the guidelines below. 1. place the external capacitors as close to the ic as possible to ensure the smallest input inductance and ground impedance. 2. place the pcb trace connecting the capacitor between vdd and gnd very close to the ic. 3. keep the agnd for the i 2 c wire clean and away from pgnd. 4. place the i 2 c wire in parallel.
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path MP2661 rev. 1.03 www.monolithicpower.com 34 4/9/2018 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2018mps. all rights reserved. typical application circuit figure14: MP2661 typical application circuit with 5v input
MP2661 ? 0.5a, 1-cell charger w/ i 2 c control and power path notice: the information in this document is subject to change with out notice. please contact mps for current specifications. users should warrant and guarantee that third party intellectual property rights ar e not infringed upon when integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP2661 rev. 1.03 www.monolithicpower.com 35 4/9/2018 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2018 mps. all rights reserved. package information wlcsp-9 (1.55mmx1.55mm)

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